Launched in 2004, dmesgd aims to provide a user-submitted repository of searchable *BSD dmesgs. The dmesg(8) command displays the system message buffer's content, and during boot a copy is saved to /var/run/dmesg.boot. This buffer contains the operating system release, name and version, a list of devices identified, plus a whole host of other useful information. We hope others find this resource useful and further contribute to its growth. Contact us at [ admin at lists dot nycbug dot org ]. Note that this site is not a substitute for sending the dmesg directly to the respective project.
Date: 2024-05-29 10:50:49
From: jj
Description: Edgerouter ER-8-XG Infinity
[ using 772200 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2024 OpenBSD. All rights reserved. https://www.OpenBSD.org OpenBSD 7.5-current (GENERIC.MP) #143: Tue May 28 21:35:10 MDT 2024 [_EMAIL_XXXXXXXXXXXXXXXXX]:/usr/src/sys/arch/octeon/compile/GENERIC.MP real mem = 17179869184 (16384MB) avail mem = 17003462656 (16215MB) random: good seed from bootblocks mainbus0 at root: board 20020 rev 1.15, model cavium,ebb7304 cpu0 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu0: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu1 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu1: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu2 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu2: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu3 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu3: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu4 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu4: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu5 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu5: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu6 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu6: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu7 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu7: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu8 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu8: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu9 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu9: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu10 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu10: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu11 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu11: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu12 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu12: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu13 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu13: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu14 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu14: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way cpu15 at mainbus0: CN72xx/CN73xx CPU rev 0.3 1800 MHz, CN72xx/CN73xx FPU rev 0.0 cpu15: cache L1-I 78KB 39 way D 32KB 32 way, L2 8192KB 8 way clock0 at mainbus0: int 5 octcrypto0 at mainbus0 octrtc0 at mainbus0: DS1337 iobus0 at mainbus0 simplebus0 at iobus0: "soc" octcit0 at simplebus0 "bootbus" at simplebus0 not configured com0 at simplebus0: ns16550a, 64 byte fifo com0: console com1 at simplebus0: ns16550a, 64 byte fifo com1: probed fifo depth: 0 bytes octgpio0 at simplebus0: 32 pins, xbit 0 octsmi0 at simplebus0 octsmi1 at simplebus0 ogxnexus0 at simplebus0 ogx0 at ogxnexus0: no phy found ogx1 at ogxnexus0: no phy found ogx2 at ogxnexus0: no phy found ogx3 at ogxnexus0: no phy found ogxnexus1 at simplebus0 ogx4 at ogxnexus1: no phy found ogx5 at ogxnexus1: no phy found ogx6 at ogxnexus1: no phy found ogx7 at ogxnexus1: no phy found ogxnexus2 at simplebus0 ogx8 at ogxnexus2: SGMII, address [_MAC_XXXXXXXXXX] atphy0 at ogx8 phy 1: AR8035 10/100/1000 PHY, rev. 4 "i2c" at simplebus0 not configured "i2c" at simplebus0 not configured octmmc0 at simplebus0 sdmmc0 at octmmc0: 8-bit, mmc high-speed sdmmc1 at octmmc0: 8-bit, mmc high-speed "spi" at simplebus0 not configured octxctl0 at simplebus0: DWC3 rev 0x280a xhci0 at octxctl0, xHCI 1.0 usb0 at xhci0: USB revision 3.0 uhub0 at usb0 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1 octxctl1 at simplebus0: DWC3 rev 0x280a xhci1 at octxctl1, xHCI 1.0 usb1 at xhci1: USB revision 3.0 uhub1 at usb1 configuration 1 interface 0 "Generic xHCI root hub" rev 3.00/1.00 addr 1 "ocla0" at simplebus0 not configured "ocla1" at simplebus0 not configured "ocla2" at simplebus0 not configured "ocla3" at simplebus0 not configured "ocla4" at simplebus0 not configured "vrm0" at simplebus0 not configured octrng0 at iobus0 base 0x1400000000000 irq 0 octpcie0 at iobus0: 4 ports octpcie0 port 0: reset timeout octpcie0 port 1: reset timeout octpcie0 port 2: reset timeout octpcie0 port 3: reset timeout uhub2 at uhub1 port 1 configuration 1 interface 0 "Genesys Logic USB2.0 Hub" rev 2.00/88.32 addr 2 umodem0 at uhub2 port 2 configuration 1 interface 0 "Ubiquiti Networks Inc. Infinity UI" rev 2.00/2.00 addr 3 umodem0: data interface 1, has no CM over data, has no break umodem0: status change notification available ucom0 at umodem0: usb1.1.00002.1 ugen0 at uhub2 port 4 "Atheros Communications product 0x3004" rev 1.10/0.01 addr 4 scsibus0 at sdmmc0: 2 targets, initiator 0 sd0 at scsibus0 targ 1 lun 0: <Sandisk, SEM04G, 0000> removable sd0: 3776MB, 512 bytes/sector, 7733248 sectors sdmmc1: can't enable card vscsi0 at root scsibus1 at vscsi0: 256 targets softraid0 at root scsibus2 at softraid0: 256 targets root on sd0a (e819bd58134f864b.a) swap on sd0b dump on sd0b WARNING: bad clock chip time WARNING: CHECK AND RESET THE DATE! WARNING: can't update clock chip time